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dictionary:bus_width [2007/11/17 18:43] (current) – created - external edit 127.0.0.1
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 +The number of data bits that can be input or accessed simultaneously. Common bus widths of DRAM are 32, 36, 40, 64, 72 and 80 bits. See BUS.
dictionary/bus_width.txt · Last modified: 2007/11/17 18:43 by 127.0.0.1