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dipcoref4 [2018/09/03 23:44] antichambre |
dipcoref4 [2018/09/04 16:58] antichambre [PCB] |
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<WRAP group> | <WRAP group> | ||
<WRAP column 50%> | <WRAP column 50%> | ||
- | {{ :antichambre:1808_dipcore_v1.beta_top.png |}} | + | {{ :antichambre:1809_dipcoreF4_v1.beta_top.png |}} |
\\ | \\ | ||
- | {{ :antichambre:1808_dipcore_v1.beta_bottom.png |}} | + | {{ :antichambre:1809_dipcoreF4_v1.beta_bottom.png |}} |
</WRAP> | </WRAP> | ||
<WRAP column 45%> | <WRAP column 45%> | ||
Line 47: | Line 47: | ||
<WRAP column 50%> | <WRAP column 50%> | ||
Top copper | Top copper | ||
- | {{ :antichambre:1808_dipcore_v1.beta_layer_top.png |}} | + | {{ :antichambre:1809_dipcoreF4_v1.beta_layer_top.png |}} |
\\ | \\ | ||
Internal 1 | Internal 1 | ||
- | {{ :antichambre:1808_dipcore_v1.beta_layer_int1.png |}} | + | {{ :antichambre:1809_dipcoreF4_v1.beta_layer_int1.png |}} |
\\ | \\ | ||
Internal 2 | Internal 2 | ||
- | {{ :antichambre:1808_dipcore_v1.beta_layer_int2.png |}} | + | {{ :antichambre:1809_dipcoreF4_v1.beta_layer_int2.png |}} |
\\ | \\ | ||
Bottom | Bottom | ||
- | {{ :antichambre:1808_dipcore_v1.beta_layer_bottom.png |}} | + | {{ :antichambre:1809_dipcoreF4_v1.beta_layer_bottom.png |}} |
</WRAP>\\ | </WRAP>\\ | ||