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====== dipCoreF4 ====== {{ :antichambre:fichier_29-08-2018_18_32_51.png?400 |}} **A reduced Core for your MIDIbox App, an STM32F405RG in a DIP40 format.** \\ \\ ===== Features ===== * MIOS32 uses same processor family and drivers(no deep change). * Same internal hardware as Disco or wCore (speed, memory, peripherals, etc...) . * Board pinout and package compatible with a MIOS8 PIC 8-) * USB connector onboard. * 5V power input and led. * 3.3V regulator and led on board. * 74HCT541 on board for the 5V output ports. * User and Reset buttons. * 2 user leds. * 8 extra pins for USB, buttons and leds. * Your favorite Core is now a current component easy to integrate. All commons MIOS32 ports are available except: * General purpose J10x ports were removed. * LCD port was reduced to a serial one, no more pins J15.D0-D7 , no back-light power supply. * 2 UART only(2 MIDI In/2Out). * 2 AIN channels only(e.g. pedal inputs) Check the [[dipboardF4|dipBoardF4]] for more details :-P \\ \\ ===== Download ===== dipCoreF4 eagle lib for easy integration in your design. <wrap download> {{ :antichambre:dipcoref4_beta.zip |}} </wrap> ---- ===== PCB ===== <WRAP group> <WRAP column 50%> {{ :antichambre:1809_dipcoreF4_v1.beta_top.png |}} \\ {{ :antichambre:1809_dipcoreF4_v1.beta_bottom.png |}} </WRAP> <WRAP column 45%> 4 layers PCB design.\\ Fits 4 layer mostly common design rules. * min. drill 10mil * min. width 5mil </WRAP>\\ </WRAP>\\ \\ <WRAP column 50%> Top copper {{ :antichambre:1809_dipcoreF4_v1.beta_layer_top.png |}} \\ Internal 1 {{ :antichambre:1809_dipcoreF4_v1.beta_layer_int1.png |}} \\ Internal 2 {{ :antichambre:1809_dipcoreF4_v1.beta_layer_int2.png |}} \\ Bottom {{ :antichambre:1809_dipcoreF4_v1.beta_layer_bottom.png |}} </WRAP>\\ ---- ===== Pinout ===== === First, was a chart. === This chart gives you the equivalence between the different pinout and functions.\\ <WRAP group> <WRAP column 80%> {{:antichambre:pinout_compare_chart2.png|}} </WRAP> <WRAP column> {{ :antichambre:pinout_compare_chart.png?120 |}} <wrap download> [[https://www.dropbox.com/s/5jc3smxbg7hxno0/1809_dipCoref4_PinoutsAndFunctions.xls?dl=1|xls chart]] </wrap> </WRAP> </WRAP> \\ === The dipCoreF4 and the legacy MIOS32 ports. === <WRAP group> <WRAP column 90%> Check [[dipboardf4|dipBoardF4]] for more details about the connectors. {{:antichambre:1808_dipcore_v1.beta_docu.png|}} </WRAP> </WRAP> \\ ===== 407VG vs 405RG ===== <WRAP group> <WRAP column 60%> === Legacy STM32F407 and 405 share the same characteristics. === {{:antichambre:stm32f407_vs_405.png|}} </WRAP> <WRAP column 35%> The 405RG is a TQFP64, a 10x10mm package and only 64 pins.\\ \\ No Ethernet MAC and camera interface.\\ \\ </WRAP> </WRAP> [[https://www.st.com/en/microcontrollers/stm32f4-series.html?querycriteria=productId=SS1577|ST STM32F4xx series]] \\ \\ === In MIOS32 === We use the same peripheral drivers same family, some compilation defined conditions were added for the specific pinout and type, number of ports. <wrap round todo 7%>toDo</wrap>\\ \\ \\
