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mb_olre16 [2016/09/23 20:18] – [GrayScale Clock] psykhazemb_olre16 [2019/04/21 08:50] (current) – [GrayScale Clock] antichambre
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 We expect 16 RGB LED rings encoders. So let's do the math : We expect 16 RGB LED rings encoders. So let's do the math :
 **16 Encoders * 32 LEDs * 3 colors = __1536 lines__ ** \\ **16 Encoders * 32 LEDs * 3 colors = __1536 lines__ ** \\
-Let's transpose this to a classical matrixed SRIO chain design:  +Let's transpose this to a classical matrixed SRIO chain design: \\ 
-**3x16=48 inputs + 32 outputs = __6*DIN + 4*DOUT__ **\\ +** 16 * 3 (cathodes) * 32 (anodes)** \\ 
 +**= 48 inputs + 32 outputs ** \\ 
 +**= __6*DIN + 4*DOUT__ **\\
 ==== Core-External Driving Concept : TLC5958 ==== ==== Core-External Driving Concept : TLC5958 ====
  
-In theory it's possible to drive such a SRIO setup but in fact buses and resistors/R networs are very hard to place and will consume a lot of process. \\ +In theory it's possible to drive such a SRIO setup but in fact buses and resistors/R networks are very hard to place and it will consume a lot of contant refresh process. \\ 
 \\ \\
 After a look on the different brands and models of LED driver IC **[[http://www.ti.com/product/TLC5958|Texas Instruments TLC5958]]** appeared as a good compromise to drive a lot of RGB LEDs without overloading the core. Designed to be a LED Display driver, its original purpose and features would allow large-sized RGB-LED-based display setups\\ After a look on the different brands and models of LED driver IC **[[http://www.ti.com/product/TLC5958|Texas Instruments TLC5958]]** appeared as a good compromise to drive a lot of RGB LEDs without overloading the core. Designed to be a LED Display driver, its original purpose and features would allow large-sized RGB-LED-based display setups\\
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 ==== Data Transfer ==== ==== Data Transfer ====
      
-A serialized design has been chosen to provide data to TLC. Prototype feature only 2 steps but the CORE works like there's 4 modules of 16 steps connected. In order to benchmark reactivity and Transfer time, Core send data for 4 modules. Through an emulated software SPI bus, for this 64 rings Data Sending __takes less than 5ms__ . Different colors and patterns like relative value(-64/63), keyboard(B&W keys) etc... were tested.\\+A serialized design has been chosen to provide data to TLC. Prototype feature only 2 steps but the CORE works like there's 4 modules of 16 steps connected. In order to benchmark reactivity and Transfer time, Core send data for 4 modules(4*16*32*3*16bit=12KBytes). Through an emulated software SPI bus, for this 64 rings Data Sending __takes less than 5ms__ . Different colors and patterns like relative value(-64/63), keyboard(B&W keys) etc... were tested.\\
  
 {{antichambre:img_3658.jpg?300|}}{{:antichambre:img_3657.jpg?300|}}{{antichambre:img_3656.jpg?300|}}\\ {{antichambre:img_3658.jpg?300|}}{{:antichambre:img_3657.jpg?300|}}{{antichambre:img_3656.jpg?300|}}\\
 {{antichambre:large.img_3754.jpg?300|}}   {{:antichambre:large.3653bd.jpeg?460|}}\\ {{antichambre:large.img_3754.jpg?300|}}   {{:antichambre:large.3653bd.jpeg?460|}}\\
- 
 ==== GrayScale Clock ==== ==== GrayScale Clock ====
  
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 **Frame update is needed only when a change occurs, TLC keep all the frame in memory and continue to distribute it to the 32 addresses lines and 16 rgb leds by address **  **Frame update is needed only when a change occurs, TLC keep all the frame in memory and continue to distribute it to the 32 addresses lines and 16 rgb leds by address ** 
 \\ \\
 +
  
 ==== GrayScale Clock ==== ==== GrayScale Clock ====
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 The TLC needs a GrayScale Clock(GSCLK) and additional control to multiplex 32 addresses (named COMSELx in diagram). The GSCLK signal should be 257 pulses + 1.5~2.5µs of interval between segments . COMSEL management needs 32 multiplexing adress lines for (5 bits coded and decoded directly on the top board).\\ The TLC needs a GrayScale Clock(GSCLK) and additional control to multiplex 32 addresses (named COMSELx in diagram). The GSCLK signal should be 257 pulses + 1.5~2.5µs of interval between segments . COMSEL management needs 32 multiplexing adress lines for (5 bits coded and decoded directly on the top board).\\
  
-=== Clock Schematic ===+=== Clock Schematic version 1 === 
 +\\ 
 +<wrap center round important 60%> 
 +//Note: This circuit is replaced by a simulated one, on a CPLD.// 
 +</wrap>
  
 {{:antichambre:tlc_gsclk.png?800|}}\\ {{:antichambre:tlc_gsclk.png?800|}}\\
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 CORE provides a regular Clock with PWM @2MHz .The 12bit counter U16 counts until 257 and trigs U1 wich is a monostable, U1 switchs, resets the counter and stops the clock counter input by U17(D-Flipflop). \\ CORE provides a regular Clock with PWM @2MHz .The 12bit counter U16 counts until 257 and trigs U1 wich is a monostable, U1 switchs, resets the counter and stops the clock counter input by U17(D-Flipflop). \\
 \\ \\
-After a certain time given by the RC couple on U1, U1 switch back and restarts the counter.+After a certain time given by the RC couple on U1, U1 switchs back and restarts the counter.
 By this way we are sure to count the exact 257 Clocks needed and the interval between 2 segments is fixed by the trimpot U19.\\ By this way we are sure to count the exact 257 Clocks needed and the interval between 2 segments is fixed by the trimpot U19.\\
 \\ \\
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 ADDR_CLK is the multiplexed lines clock . It's used to gate the PWM signal and obtain the GSCLK and of course, as a clock for the ADDR Counter U5. The counter U5 provides the coded ADDR_x lines and an EOF(End Of Frame) when 32 is reached.\\ ADDR_CLK is the multiplexed lines clock . It's used to gate the PWM signal and obtain the GSCLK and of course, as a clock for the ADDR Counter U5. The counter U5 provides the coded ADDR_x lines and an EOF(End Of Frame) when 32 is reached.\\
  
 +
 +=== Clock version 2 ===
 +
 +<wrap center round todo 60%>
 +CPLD/FPGA version
 +</wrap>
  
  
mb_olre16.1474661936.txt.gz · Last modified: 2016/09/23 20:18 by psykhaze