pad_4_4
Differences
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pad_4_4 [2016/08/10 22:32] latigid_on [Versions] |
pad_4_4 [2018/03/05 22:57] (current) latigid_on [Assembly] |
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| - | ===== BOM v1.2 ===== | + | ===== BOM v1.1 ===== |
| ^Type ^Qty ^Value ^Package ^Parts^Notes^ | ^Type ^Qty ^Value ^Package ^Parts^Notes^ | ||
| Line 38: | Line 38: | ||
| | |16|WS2812B|5mm|programmable LEDs| | | |16|WS2812B|5mm|programmable LEDs| | ||
| ^headers^ | ^headers^ | ||
| - | | |4| |2*5 (shrouded) SMT|J2-5| | + | | |4| |2*5 (shrouded) SMT|J2-5|can use DIL 100mil breakaway header strips| |
| | |1| |1X03_SMALL|J1| can use Molex 22-23-2031| | | |1| |1X03_SMALL|J1| can use Molex 22-23-2031| | ||
| ^switches^ | ^switches^ | ||
| Line 49: | Line 49: | ||
| ===== Versions ===== | ===== Versions ===== | ||
| - | v1.1: current release. Some traces moved around, grounding error fixed. J1 power header changed to offset pads so an SMT header may be soldered if desired. | + | v1.1: current release. Some traces moved around, grounding error fixed. J1 power header changed to offset pads so an SMT pinheader may be soldered if desired. \\ |
| v1.0: errata: J4 and J5 have no connection to ground. J1-3 do carry ground, so it isn't a problem if the DIN/DOUT modules share the same power rail. | v1.0: errata: J4 and J5 have no connection to ground. J1-3 do carry ground, so it isn't a problem if the DIN/DOUT modules share the same power rail. | ||
| ===== Assembly ===== | ===== Assembly ===== | ||
| - | Putting the board together is simple. As usual, start with the flattest components and work your way up. | + | To keep the button pad flat, it's best to solder all components on the rear of the board i.e. opposite the pads. The contacts are exposed ENIG, so try not to damage the surface by scratching or splashing solder/flux on them.\\ |
| - | ==== Resistors ==== | + | Start by tinning one pad (preferably not the pad joined to the ground plane with thermals) of each 1206 capacitor, making a "tack" joint, aligning the part and cleaning up if needed.\\ |
| - | * four 30k resistors marked in pink | + | The best way to fix the 1N4148 diodes is to place the parts then solder **from the same side** just the anode lead that intersects the pLED silkscreen. (The length of this lead isn't important as the LED will not be flush on the top face. Don't short out any pins though!) Turn the board around and clip the cathode lead as close to the board as possible. You can even pull the loose lead out slightly as long as you can still make a solid joint. On the **rear** of the board, solder the cathode with as little solder as possible. The aim is to leave no solder bump on the frontside. Try to give equal care to the other through hole components (R1, C1, D1, J1). |
| - | * remainder are 49k9 | + | |
| - | * for best results, match R1/R2, R7/R8 (and so on), and R4/R5/R6, R10/R11/R12 (and so on). | + | |
| - | * the value is less important than the minimum deviation. | + | |
| - | {{:ain_4_30k_resistors.png?nolink&300|}} | + | Check that the pinout of your pLEDs matches with the board i.e. serial in on the rounded side, serial out on the flattened side. Also test the height relative to the silicone button pad; it's not necessary to push the leads in the whole way (and you might damage your LED). |
| - | ==== Capacitors ==== | + | If using shrouded headers, ensure the notch points out on the same side as the pin 1 designator. |
| - | * four 10p as marked in pink | ||
| - | * electrolytics in yellow | ||
| - | * blue are optional (i.e. probably unnecessary) | ||
| - | * remainder are 100n. | ||
| - | {{:ain_4_10pf.png?nolink&300|}} | ||
| - | ==== Power ==== | + | ==== Interconnections ==== |
| - | * J2 is a standard Eurorack header | + | * J2 normally connects to Core J4B (I2C) |
| - | * red = -12V | + | * J3 carries the WS2812B chain for additional modules |
| - | * blue = +12V | + | * J4 connects to a DIN header |
| - | * green = 0V(ground) | + | * J5 connects to a DOUT header |
| - | * for Core power, bridge the solder jumper marked in yellow | + | |
| - | * otherwise install the Vreg circuit in pink | + | |
| - | * **IMPORTANT** only choose one of these 3v3 power options! Don't install the regulator if the solder jumper is bridged. | + | |
| - | {{:ain_4_power_rails.png?nolink&300|}} | ||
| - | ==== Headers ==== | + | ===== License ===== |
| - | + | ||
| - | For connection to a [[Control Board]], use pin headers placed on the opposite side as the rest of the components i.e. follow the silkscreen markings. For standalone use, you probably want header pins (or sockets, or even bare wires if you wish) on the same side as the remaining circuitry. | + | |
| - | + | ||
| - | ---- | + | |
| - | + | ||
| - | + | ||
| - | ==== Standalone use ==== | + | |
| - | + | ||
| - | For simplest results, use the complementary [[Control Board]]. Otherwise see below for header functions. | + | |
| - | + | ||
| - | + | ||
| - | === Five pin header === | + | |
| - | + | ||
| - | * IN = CV input | + | |
| - | * for scaling bipolar CVs, connect or switch into OFFSET (e.g. +5V; n.b. the offset should be referenced to the common 0V) | + | |
| - | * for 0-5V operation, leave SWITCH open; for 0-10V operation, jumper or switch in COMMON to POLE | + | |
| - | + | ||
| - | {{:ain_4_sil_1.png?nolink&300|}} | + | |
| - | + | ||
| - | + | ||
| - | + | ||
| - | + | ||
| - | === Three pin header === | + | |
| - | + | ||
| - | * with a 100k pot facing you, solder the left leg to 0V(ground) | + | |
| - | * centre to WIPER | + | |
| - | * right to LEG | + | |
| - | * WIPER and LEG may be jumpered if pots aren't desired, but it is quite useful to have an attenuator to trim down variable CVs or even clip the second op amp for crunchy waveforms! | + | |
| - | + | ||
| - | {{:ain_4_sil_2.png?nolink&300|}} | + | |
| - | ---- | + | |
| - | + | ||
| - | ==== Interconnection to Core ==== | + | |
| - | + | ||
| - | J1 carries the scaled CV to J5A or J5B of an STM32F4 Core module. | + | |
| - | ---- | + | |
| - | + | ||
| - | + | ||
| - | + | ||
| - | ==== License ==== | + | |
| Currently the design is (c) 2016 antilog devices with all rights reserved; all documentation is CC BY-NC-SA 3.0. | Currently the design is (c) 2016 antilog devices with all rights reserved; all documentation is CC BY-NC-SA 3.0. | ||
pad_4_4.1470868347.txt.gz · Last modified: 2016/08/10 22:32 by latigid_on
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